Senior Verification Engineer (UVM/SystemVerilog) w Warszawa, Polska

Expected, UVM, SystemVerilog

Optional, C, C++, Python, SystemC

This is how we work, at the client's site

Your responsibilities, Perform the full range of functional verification activities., Develop verification environments from scratch, including drivers, monitors, scoreboards, and coverage models., Integrate Verification IPs (VIPs) for protocols such as DDR, PCIe, and AXI., Define and implement verification sequences for complex control-flow scenarios., Gain a system-level understanding of products with strong hardware-software interaction., Integrate and maintain reference models., Define and execute test plans., Establish verification methodologies, flows, and supporting infrastructure.

At least 5 years of verification experience., Proven ability to build verification environments from the ground up., Experience with UVM and SystemVerilog., Strong knowledge of Verification IPs and industry-standard protocols, including PCIe, DDR, and AXI.

Optional, Understanding of hardware-software interaction., Experience with C, C++, Python, or SystemC.

SQUARE ONE RESOURCES sp. z o.o., At Square One Poland we link IT experts with the business. With over 25 years of experience, we specialize in recruitment processes on a global scale. Despite years of experience, we still have a startup DNA and this is our advantage. Our offices are located in London and Warsaw, however, we can reach clients from all over the world, from start-ups to big worldwide corporations.

This is how we work,